1. Technical Field
The present invention relates to a method and an apparatus for transmitting signals, and more particularly, to a method and an apparatus for selectively transmitting a command signal and an address signal. Furthermore, the present invention relates to a register for buffering a command signal and an address signal in a memory module accessed by a memory controller, a memory module including a register, and a system thereof.
2. Description
FIG. 1 is a block diagram of a system for transmitting signals. Referring to FIG. 1, a system 10 includes a memory controller 20 and a plurality of memory modules 30, 40, 50, and 60.
The memory modules 30, 40, 50, and 60 are realized as dual in-line memory modules (DIMMs), and are inserted into corresponding slots (not shown) of the system.
The memory controller 20 outputs a command signal COM including a row address strobe (RAS), a column address strobe (CAS), a write enable signal (WE), a plurality of select signals CS1, CS2, CS3, and CS4, and an address signal ADD to the plurality of DIMMs 30, 40, 50, and 60 via a predetermined bus. Here, each of the select signals CS1, CS2, CS3 and CS4 is a signal for accessing ranks or memory modules. The rank denotes a selected group of a plurality of semiconductor devices mounted on a memory module in response to one of the select signals CS1, CS2, CS3 and CS4.
The DIMM 30 may be formed of one or more ranks according to the type of the DIMM 30. On the other hand, the DIMM 30 includes DRAMs and a register, regardless of the number of the ranks.
FIG. 2 illustrates a DIMM including a conventional register. Referring to FIGS. 1 and 2, the DIMM 30 includes memory devices as DRAMs 31a1, 31a2, 31am, and 31an, a register 33, and a phase locked loop (PLL) 80.
Since the circuitry 30b on a rear surface of the DIMM 30 may be different from the circuitry 30a on a front surface of the DIMM 30 according to the kind of the DIMM 30, only the circuitry 30a on the front surface of the DIMM 30 is illustrated for convenience in description.
The arrangements of the DIMMs 40, 50, and 60 are the same as the arrangement of the DIMM 30, which can be conveniently understood from the arrangement of the DIMM 30.
The PLL 80 generates a plurality of clock signals PCLK and OPCLK whose phases are locked to the phase of a clock signal CLK. Here, one clock signal PCLK of the clock signals PCLK and OPCLK is input to a first latch 73 and a second latch 74 of the register 33a. 
The other clock signals OPCLK are used for a predetermined memory device.
A command signal COM, a plurality of select signals CS1, CS2, CS3, and CS4 and an address signal ADD output from the memory controller 20 are transmitted via a predetermined bus to each register 33, 43, 53, and 63 of each of the DIMMs 30, 40, 50, and 60.
Here, each register 33, 43, 53, and 63 in the DIMMs 30, 40, 50, and 60 has a buffer 71, a second buffer 72, a first latch 73, and a second latch 74 respectively.
The first buffer 71 receives the command signal COM and the address signal ADD and buffers the signals, and the second buffer 72 receives and buffers the select signal CS1.
The first latch 73 transmits the buffered command signal and address signal to memory devices 31a1, 31a2, . . . , 31am, and 31an in the DIMMs 30, 40, 50, and 60, in response to the clock signal PCLK and the second latch 74 transmits the buffered select signal to the memory devices 31a1, 31a2, . . . , 31am, and 31an in the DIMMs 30, 40, 50, and 60, in response to the clock signal PCLK. The memory devices 31a1, 31a2, . . . , 31am, and 31 in the DIMMs 30 are selected in response to the select signal CS1.
Referring to FIGS. 1 and 2, although the system 10 including four DIMMs 30, 40, 50, and 60, intends to access a first rank 61a of the DIMM 60, the command signal COM and the address signal ADD output from the memory controller 20 are transmitted to each DIMM 30, 40, 50, and 60 via the predetermined bus. Therefore, the predetermined bus connected between the register 33 and the memory devices 31a1, 31a2, . . . , 31am, and 31an in the DIMMs 30, 40, and 50 consumes electric power in response to toggling the command signal COM and the address signal ADD.
Accordingly, the registers 33, 43, and 53 corresponding to the DIMMs 30, 40, and 50, respectively, which do not need to be accessed, are activated so that each latch 73 transmits the buffered command signal and the address signal to the DRAMs of each DIMM 30, 40, and 50, via the predetermined bus 35 in response to the clock signal PCLK.
Consequently, the predetermined buses connected between the memory devices and the registers 33, 43, and 53 in the corresponding DIMMs 30, 40, and 50 respond to the toggling command signal and address signal, thereby consuming electric power.
Since the registers mounted on the memory modules which are not accessed also output to their output terminals the toggling command signal and address signal received at their input terminals, the toggling command signal and address signal are transmitted to bus provided on the memory modules. As a result, the system consumes a large amount of electric power.
To solve the above-described problem, it would be desirable to provide a method and an apparatus for transmitting a command signal and an address signal selectively to reduce electric power consumption.
To accomplish the above objective, a method for transmitting a command signal and an address signal to a rank which is accessed, includes receiving and buffering the command signal and the address signal, and transmitting the buffered command signal and address signal to the rank in response to a clock signal and a select signal for accessing the rank.
Transmitting the buffered command signal and address signal to the rank includes latching the buffered command signal and address signal in response to the select signal, and transmitting the latched command signal and address signal to the first semiconductor device in response to the clock signal.
In addition, a method for transmitting a command signal and an address signal to a first memory module which is accessed, includes receiving and buffering the command signal and the address; and transmitting the buffered command signal and address signal to the memory devices in response to a clock signal and a select signal for accessing the memory devices.
Here, transmitting the buffered command signal and address signal to the plurality of semiconductors includes latching the buffered command signal and address signal in response to the select signal, and transmitting the latched command signal and address signal to the first memory module in response to the clock signal.
To accomplish the above objective, a register mounted on a memory module, for transmitting a command signal and an address signal to a rank mounted on the memory module which is to be accessed, includes a buffer adapted to receive and buffer the command signal and the address signal; and a latch adapted to transmit the buffered command signal and address signal to the rank, in response to a clock signal and a select signal for accessing the rank.
In addition, the latch includes a first latch adapted to latch the buffered command signal and address signal in response to the select signal, and a second latch adapted to transmit the latched command signal and address signal to the first semiconductor device in response to the clock signal.
To accomplish the above objective, a register is provided for transmitting a command signal and an address signal to a plurality of memory devices which are to be accessed. The register includes a buffer adapted to receive and buffer the command signal and the address; and a latch adapted to transmit the buffered command signal and address signal to the memory devices in response to a clock signal and a select signal for selecting the memory devices.
To accomplish the above objective, a memory module includes a plurality of memory devices and a register adapted to receive and buffer a command signal and an address signal and adapted to transmit the buffered command signal and address signal to the memory devices which are to be accessed.
Here, the register includes: a buffer adapted to receive and buffer the command signal and the address signal; a first latch, connected to the buffer, adapted to latch the buffered command signal and address signal in response to a select signal for accessing the memory devices; and a second latch adapted to transmit an output signal of the first latch to the memory devices in response to a clock signal.
To accomplish the above objective, a system includes: a memory controller adapted to output a address signal, a command signal and a select signal; a plurality of memory modules; and a bus adapted to transmit the address signal, the command signal and the select signal to each memory module, wherein each of the memory modules includes a plurality of memory devices; and a register adapted to receive and buffer the command signal and the address signal and adapted to transmit the buffered command signal to the memory devices which are to be accessed, in response to the select signal for accessing the memory devices.
To accomplish the above objective, a system includes: a memory controller adapted to output an address signal, a command signal and a select signal; a plurality of memory modules; and a bus adapted to transmit the address signal, the command signal and the select signal to each memory module, wherein each of the memory modules includes a register adapted to receive and buffer the command signal and the address signal and adapted to transmit the buffered command signal to the memory devices which is to be accessed, in response to the select signal for accessing the memory devices.
A system as disclosed herein includes a memory controller adapted to output an address signal and a command signal including a select signal, a plurality of memory modules, and a bus adapted to transmit the command signal to each memory module. Here, each of the memory modules includes a plurality of memory devices and a register adapted to receive and buffer the command signal and the address signal. In response to the select signal for accessing a first memory device, the register transmits the buffered command signal to the first memory device.